FIG. 5 is a block diagram showing a liquid crystal display device in which a plurality of source lines are driven by dividing, using switches, one output (signal voltage) from a source driver.
As in the figure, on the surface of a display section 195 of the liquid crystal display device, a plurality of gate lines G190, G191, . . . provided in crosswise and a plurality of source lines SR101, . . . , SB112, . . . provided in lengthwise are laid out in a matrix manner. For instance, at the respective intersections of the gate line G191 and the source lines TR125 through TB136, then-film transistors TR125 through TB136 are formed as switching elements.
The gates of the respective thin-film transistors TR125 through TB136 are connected to the gate line G191, and the sources of the respective thin-film transistors TR125 through TB136 are connected to the corresponding source lines SR101 through SB112. The drains of the respective thin-film transistors TR125 through TB136 are connected to corresponding pixel electrodes PR113 through PB124.
Every six source lines are grouped as one block (B154, B155), and the source lines in one block are connected to an output (S160 or S161) of a source driver 170, via dividing switches SWR137 though SWB148 that are, for instance, transistors and are provided on the respective source lines SR101 through SB112.
For instance, in the block B154, six source lines SR101, SG102, SB103, SR104, SG105, and SB106 are connected to the drains of the dividing switches SWR137, SWG138, SWB139, SWR140, SWG141, and SWB142, respectively. The sources of these dividing switches SWR137 though SWB142 are connected to one output S160 of the source driver 170, the output S160 corresponding to the block B154. Also, the gates of the dividing switches SWR137 through SWB142 are connected to six dividing switch lines SWL149, SWL150, SWL151, SWL152, SWL153, and SWL154, respectively.
In the display section 195 being thus arranged, the dividing switches SWR137 through SWR148 are sequentially turned on, in the meanwhile one gate line (either G190 or G191) is in the state of selection (on state). With this, the output (signal voltage, either S160 or S161) from the source driver 170 is sequentially written into pixel electrodes PR113 through PB124.
The following will specifically describe a conventional method of driving the above-described display section 195, in reference to FIGS. 5 and 6.
FIG. 6 is a timing chart regarding the block 155, on the occasion of displaying a uniform color, e.g. a halftone, on the whole screen. In the figure, a reference sign T indicates one horizontal period (a period for scanning one gate line). It is also noted that the figure relates to three horizontal periods (periods for scanning three gate lines including the gate lines G190 and G191).
That is to say, during the period T, the signal voltage S161 is sequentially supplied from the source driver 170 to six source lines SR107 through SB112 of the block B155. With this, the signal voltage S161 is sequentially written into the pixel electrodes PR119 through PB124 of the block B155. Furthermore, in synchronism with the above, the signal voltage S160 is written into the pixel electrodes PR113 through PB118 of the block B154. As a result, during the period T, the signal voltages (S160, S161 and the like) supplied from the source driver 170 are written into all of the pixel electrodes (PR113, . . . ) connected to the gate line G191.
It is noted that each of the signal voltages with which the source lines (SR107 through SB112) and the pixel electrodes (PR119 through PB124) are charged has a driving waveform such as S161 (shown at the top of FIG. 6). In the above-described driving method, the polarity of the signal voltage S161 is reversed in each horizontal period T.
As illustrated in FIGS. 5 and 6, in synchronism with the selection (turn-on) of the gate line G191 at a time t0, an ON signal is supplied to the dividing switch SWR143 via the dividing switch line SWL149, and the signal voltage S161 is supplied from the source driver 170 to the source line SR107. On this occasion, the polarity of the voltage on the source line SR107 is caused to be in reverse to the polarity of the voltage that was supplied in the immediately preceding horizontal period (e.g. a period for scanning G190).
Then the signal voltage S161 having been supplied from the source driver 170 to the source line SR107 is written into the pixel electrode PR119 via the source and drain of the thin-film transistor (TR131).
Next, in synchronism with the turn-off of the dividing switch SWR143 at a time t1, the ON signal is supplied to the dividing switch SWR144 via the dividing switch line SWL150, while the signal voltage S161 is supplied from the source driver 170 to the source line SG108. Also on this occasion, the polarity of the voltage on the source line SG108 is caused to be in reverse to the polarity of the voltage supplied in the immediately preceding horizontal period. (In other words, provided that the polarity of the signal voltage S161 is positive during the times t0 through t7, the polarity of the voltage on the source line SG108 is reversed to be negative.)
Then the signal voltage S161 having been supplied from the source driver 170 to the source line SG108 is written into the pixel electrode PG120.
At a time t2, the ON signal is supplied to the dividing switch SWB145 concurrently with the turn-off of the dividing switch SWG144, and the signal voltage S161 (positive signal voltage) is supplied from the source driver 170 to the source line SB109. Then the signal voltage S161 having been supplied to the source line SB109 is written into the pixel electrode PB121.
In a similar manner, from a time t3 to a time t5, the signal voltage S161 is written into the pixel electrodes PR122 though PB124.
The above-described driving method, however, has the following drawback. That is, the voltages on the source lines SR101 through SB112 are varied on account of parasitic capacities between the source lines SR 101 through SB112, so that the voltages written into the pixel electrodes PR113 through PB124 are varied. By the way, FIG. 7 schematically shows the parasitic capacities C201 through C211 existing between the source lines (SR101 through SB112).
For instance, in the case of the source lines SR107 and SG108, the polarity is changed, at the time t0, from negative at the time of the directly preceding horizontal period to positive, and the signal voltage S161 of the source driver 170 is written into the pixel electrode PR119 (i.e. the pixel electrode PR119 is charged with the signal voltage S161) until the time t1. Note that, during this period, while the polarity of the source line SR107 is positive, the polarity of the neighboring source line SG108 has been negative since the directly preceding horizontal period.
After the dividing switch SWR143 is turned off at the time t1, the dividing switch SWG144 is turned on, and the polarity of the source line SG108 is reversed from negative to positive. In response to this, a voltage on account of a parasitic capacity (C207, see FIG. 7) between the SR107 and SG108 flows into the source line SR107 and the pixel electrode PR119. As a result, the voltages having been written into the source line SR107 and the pixel electrode PR119 are varied (overshot).
At the time t2, a voltage on account of a parasitic capacity C208 (see FIG. 7) between the source line SG108 and the source line SB109 flows into the source line SG108 and the pixel electrode PG120, so that the voltages having been written into the source line SG108 and the pixel electrode PG120 are varied (overshot). Similarly, from the time t3 to the time t5, the voltages having been written into the source lines SB109 through SG111 and the pixel electrodes PB121 through PG123 are varied (overshot).
Furthermore, at the time t5 at which the dividing switch SWB148 is turned on, the SWB142 of the block 154 is also turned on. On this occasion, the dividing switch SWR143 of the block 155 is in the off state. For this reason, when the polarity of the source line SB106 is reversed from negative to positive, a voltage on account of a parasitic capacity C206 (see FIG. 7) between the source line SB106 and the source line SR107 flows into the source line SR107 and the pixel electrode PR119, and the voltages having been written into the source line SR107 and the pixel electrode PR119 are overshot again (for the second time).
FIG. 6 schematically shows how the aforesaid voltage variations (overshoot) occur. Note that, the voltage variations are indicated by sections where the waveforms of the respective source lines (SR107 through SB112) and pixel electrodes (PR119 through PB124) are overlapped with each other.
More specifically, at the time t1, the source line SR107 (pixel electrode PR119) is overshot for the first time, and in similar manners, the first overshoots occur in the source line SG108 (pixel electrode PG120) at the time t2, in the source line SB109 (pixel electrode PB121) at the time t3, and in the source line SR110 (pixel electrode PR122) at the time t4. Moreover, at the time t5, the source line SG111 (pixel electrode PG123) is overshot for the first time and the source line SR107 (pixel electrode PR119) is overshot for the second time.
As a result of the above, in each block (B154, B155) shown in FIG. 5, a voltage which has been overshot and increased twice from the target voltage is consequently written into the pixel electrode (PR113 or PR119) that is subjected to the voltage writing at the start, and voltages which have been overshot and increased once from the target voltages are consequently written into the remaining pixel electrodes (PG114 through PR116 and PG120 through PG123), except into the pixel electrode (PB118 or PB124) that is subjected to the voltage writing at the last.
On account of this, a striped pattern appears vertically (i.e. along the source lines) in each block, when an image is reproduced.
To solve this problem, a patent document 1 (Japanese Laid-Open Patent Application No. 11-338438/1999; published on Dec. 10, 1999, corresponding to EP1069457) discloses a method that focuses attention on the differences between transmittances of R, G, and B at a given voltage. More specifically, according to this method, three signal lines are grouped as one block (i.e. an output of one source driver is divided into three), the signal line that is selected at the start (i.e. firstly) is designated as “B” where the variation of brightness on account of voltage rise is minimum, and the signal line that is selected at the last (i.e. thirdly) is designated as “R” where the variation of brightness on account of voltage rise is maximum.
With this, even if the voltage variation on account of the parasitic capacity between the signal lines occurs, the differences between the brightness of R, G, and B can be compensated. Also, since the voltage variations in the respective signal lines are caused to be substantially equal to each other, the aforesaid voltage variation is not conspicuous.
However, the method disclosed by the patent document 1 is a technology that makes the aforesaid striped pattern on account of the voltage variation be inconspicuous by dividing the output of one source driver into three (i.e. by performing time-division) so as to determine, in consideration of the transmittances of R, G, and B at a given voltage, the colors corresponding to the respective signal lines. Therefore, this method causes the striped pattern on account of the voltage variations to be unnoticeable.
In other words, since the voltage variations on the respective signal lines are not fully eliminated, there is a limit to the improvement in the image quality.
Furthermore, to substantially equalize the voltage variations on the respective signal lines of R, G, and B, it is necessary to divide (i.e. perform time-division) the output from the source driver into three, and also to designate the first signal line as B and the third signal line as R, at the time of grouping the signal lines into blocks by setting the time-division number to be 3. It is noted that such limitations significantly decrease the design freedom of the device.
In addition to the above, a patent document 2 (Japanese Laid-Open Patent Application No. 10-39278/1998; published on Feb. 13, 1998) discloses such an arrangement that, before applying a display signal during a period in which a pixel is selected, signal voltages whose polarities are identical with that of the display signal are simultaneously applied to respective vertical lines, thereby preventing the variation of the voltage level of the display signal on account of the voltage that had been kept before the application of the display signal to liquid crystal.